This invention relates generally to the architecture of microprocessors, and, more specifically, to the structure and use of parallel instruction processing pipelines.
A multi-staged pipeline is commonly used in a single integrated circuit chip microprocessor. A different step of the processing of an instruction is accomplished at each stage of the pipeline. For example, one important stage generates from the instruction and other data to which the instruction points, such as data stored in registers on the same chip, an address of the location in memory where an operand is stored that needs to be retrieved for processing. A next stage of the pipeline typically reads the memory at that address in order to fetch the operand and make it available for use within the pipeline. A subsequent stage typically executes the instruction with the operand and any other data pointed to by the instruction. The execution stage includes an arithmetic logic unit (ALU) that uses the operand and other data to perform either a calculation, such as addition, subtraction, multiplication, or division, or a logical combination according to what is specified by the instruction. The result is then, in a further stage, written back into either the memory or into one of the registers. As one instruction is moved along the pipeline, another is right behind it so that, in effect, a number of instructions equal to the number of stages in the pipeline are being simultaneously processed.
Two parallel multi-stage pipelines are also commonly used. Two instructions may potentially be processed in parallel as they move along the two pipelines. When some interdependency exists between two successive instructions, however, they often cannot be started along the pipeline at the same time. One such interdependency is where the second instruction requires for its execution the result of the execution of the first instruction. Each of the two pipelines has independent access to a data memory through one of two ports for reading operands from it and writing results of the instruction execution back into it. The memory accessed by the pipelines is generally on the integrated circuit chip as cache memory, which, in turn, accesses other semiconductor memory, a magnetic disk drive or other mass storage that is outside of the single microprocessor integrated circuit chip.
It continues to be a goal of processor design to increase the rate at which program instructions are processed. Therefore, it is the primary object of the present invention to provide an architecture for a pipelined microprocessor that makes possible an increased instruction processing throughput.
It is another object of the present invention to provide such a pipelined microprocessor that minimizes the additional amount of power consumed and integrated circuit space required to obtain a given increase the rate of processing program instructions.